The capacity of a capacitor is related to the quality of dynamic random access memory (DRAM). The conventional simple plannar-typed capacitor is not good enough to meet the requirement of high density of DRAM. Therefore, a process for manufacturing a single-layer crown capacitor through the formation of a single insulator and a spacer is adopted in order to increase the capacity of capacitor. For example, H. Watanabe, et al. has proposed a process for forming a single-layer crown capacitor (A new cylindrical capacitor using hemispherical grained Si (HSG-Si) for 256 Mb DRAMs. (1992) IEEE). Please refer to FIG. 1 showing this process. It is briefly described as follows:
In FIG. 1 (a), a silicon dioxide layer 2 is formed over an insulator 1 (e.g. borophosphosilicate glass (BPSG) layer) by chemical vapor deposition (CVD) and then a contact window is formed in the insulator 1 and the silicon dioxide layer 2 by photolithography and etching techique. Thereafter, a polysilicon layer is formed over the contact window and the silicon dioxide layer 2 by CVD and then the polysilicon layer is partially removed by etch back to form a contact plug 31 in the contact window.
The steps shown in FIG. 1 (b) include: (1) a p-doped amorphous-Si layer is formed over the silicon dioxide layer 2 and the contact plug 31 by CVD; (2) another insulator (e.g. phosphosilicate glass (PSG) layer or a borophosphosilicate glass layer) is formed over the p-doped amorphous-Si layer by CVD; (3) portions of the p-doped amorphous-Si layer and the another insulator are removed by photolithography and etching techique while retaining the defined p-doped amorphous-Si layer 41 and another insulator 51 for forming a lower capacitor plate of the single-layer crown capacitor.
In FIG. 1 (c), another p-doped amorphous-Si layer is formed on a portion of the silicon dioxide layer 2 and the another insulator 51 as well as alongside the p-doped amorphous-Si layer 41 and the another insulator 51 by CVD. Thereafter, the another p-doped amorphous-Si layer is partially removed by dry etching while retaining a portion of the p-doped amorphous-Si layer 42 alongside the amorphous-Si layer 41 and the another insulator 51.
FIG. 1 (d) shows a step to remove the another insulator 51 by wet etching.
The steps shown in FIG. 1 (e) include: (1) a polysilicon layer is formed on a portion of the silicon dioxide layer 2 and the amorphous-Si layers 41, 42 by CVD at 560.about.580.degree. C.; (2) the polysilicon layer is processed through an anealing procedure for forming a hemispherical grained Si (HSG) to increase the surface area of the capacitor; and (3) the hemispherical grained Si is partially removed while retaining the defined hemispherical grained Si 61. Thus, the amorphous-Si layers 41, 42, the contact plug 31, and the hemispherical grained Si 61 serve as a lower capacitor plate of the single-layer crown capacitor.
In FIG. 1 (f), a dielectric layer 7 (e.g. oxide-nitride-oxide (ONO) layer) is formed over a portion of the silicon dioxide layer 2 and the hemispherical grained Si 61 by chemical vapor deposition and then a polysilicon layer 8 is formed over the dielectric layer 7 by chemical vapor deposition, wherein the polysilicon layer 8 serves as an upper capacitor plate of the single-layer crown capacitor.
However, this kind of the single-layer crown capacitor is still not good enough to solve the problem of insufficient capacitance of DRAM in the future.